A traditional non-volatile memory controller includes Error Correction Code (ECC) decoders configured to correct data from non-volatile memory devices in a memory system such as an SSD. Types of non-volatile memory include NAND flash memory, NOR flash memory, magnetic RAM (MRAM), resistive RAM (RRAM), phase change memory (PCM) and battery-backed volatile memories. For example, a multi-channel controller with N memory channels (e.g. where N may be 4, 8, 16 etc.) typically has N channel ECC decoders, one per channel, to provide high-bandwidth, independent parallel operation. The multi-channel ECC decoders form a first layer or line of ECC decoders referred to as “frontline” decoders. The frontline decoders are the first error correcting decoders that the data from the non-volatile memory devices encounter. The “frontline” decoders are capable of correcting the data frames read from the non-volatile memory devices under most circumstances, providing frames with no errors. The traditional controller may have subsequent decoders (e.g., “second-line” decoders, “third-line” decoders, “fourth-line” decoders, and so on) used in the event that the frontline decoders fail to correct all errors. Given that the subsequent decoders are not in use all the time, the subsequent decoders are typically shared among read channels used to communicate data from the non-volatile memory devices to a host. The subsequent decoders are located outside and away from the read channels. On the other hand, a dedicated frontline decoder is allocated for each read channel and is embedded or otherwise located in a respective read channel.
This traditional arrangement means that highly capable ECC resources must still be dedicated and fixed to each read channel, even if their error correcting capability is not fully employed all the time under all circumstances. For example, in the early stages of the lifecycle of non-volatile memory devices in an SSD, there may be few read errors, whereas later in the lifecycle there may be orders of magnitude more errors. Another factor is that there may be wide variations in error rates, such as between the read errors from different pages of a memory block in a non-volatile memory, between memory blocks in a single device, or between memory devices. There may also be wide variations in error rates due to temperature variations, the length of time between the time the data is first read and the time it was originally written (the retention period of the data), the number of times a block containing the data has previously been erased (the number of Program/Erase or P/E cycles), or due to the read/write activity on memory cells adjacent to the memory cells where the data is located. These variations may be compiled into sets of error characteristics and profiles for individual devices or ranges of devices. Dedicated frontline decoders with capabilities sized to cope with these variations will necessarily not have their full capabilities employed all the time, which is inefficient. There is therefore a need for a more efficient arrangement of ECC decoders under all circumstances when reading different non-volatile memory devices in an SSD.